Feedback shift register for generating digital signals representing series of pseudo-random numbers

ABSTRACT

A feedback shift register for generating digital signals representing pseudo-random number sequences has n-stages and exclusive OR-circuits in the feedback logic, as well as a clock-pulse generator. To be able to generate digital signals, which are well suited for a further digital processing, the clock-pulse generator (17) is linked with the n-stages (11, 12, 13, 14, 15) of the shift register (10) via a controllable gate circuit (18), which blocks one clock pulse of 2 n  clock pulses (CLK) of the clock-pulse generator (17) in each case.

BACKGROUND OF THE INVENTION

The present invention relates to a feedback shift register forgenerating digital signals representing pseudo-random number sequencescomprising n-stages and exclusive OR-circuits in the feedback logic, aswell as comprising a clock-pulse generator.

A. Wolf "Meβtechnik fur das BISDN" [Measuring Technique for the BISDN],VDE Publishers, 1992, pp. 72-75 or U. Tietze/Ch. Schenk"Halbleiter-Schaltungstechnik" [Semiconductor Circuit Engineering],Springer Publishers 1976, pp. 590-593 disclose one such feedback shiftregister. FIG. 1 depicts a known shift register 1 of this type thatincludes five stages 2, 3, 4, 5 and 6, each constituted by for example,a D-flip-flop. As is apparent from FIG. 1, the shift register 1 goesthrough a feedback loop, an exclusive OR-gate 7 being arranged betweenthe stages 3 and 4. The operation of this register can be expressed bythe following generator polynomial G_(KKF) (x):

    G.sub.KKF (x)=x.sup.0 +x.sup.2 +x.sup.5 =x.sup.5 +x.sup.2 +1(1)

This generator polynomial G_(KKF) (x) is a so-called irreduciblepolynomial with the degree g=5; the period of a 2⁵ -m-sequence able tobe generated with it as a pseudo-random number sequence amounts to 2^(g)-1=31.

For the sake of having a simplest possible description, neither theclock-pulse generator common to all stages nor the customary blockingprotection are depicted in the case of the known shift register shown inFIG. 1. In the case of the known shift register, all stages receive thesame clock signal, through which means the contents i₁ (x).x⁰, i₂(x).x¹, etc. of the individual stages 2 through 6 change with everyclock signal. The contents of the individual stages can be expressed bythe polynomial I(x) indicated in the following equation (2):

    I(x)=x.sup.4 ·i.sub.5 +x.sup.3 ·i.sub.4 +x.sup.2 ·i.sub.3 +x.sup.1 ·i.sub.2 +x.sup.0 ·i.sub.1( 2)

Here, the state in which all stages have a "0" contents is excluded.

In a generally known manner, the contents of the shift register make upthe rows of a binary Galois field, and can generally be expressed by thefollowing relation (3)

    x.sup.i mod G.sub.KKF (x),                                 (3)

when a "1" is input for i=0 in the first stage (x⁰). The states depictedin FIG. 2 result then for the contents of the stages 2 through 6 when ashift register in accordance with FIG. 1 is used. From x³¹ on, thestates of the individual stages 2 through 6 repeat themselves because ofthe period of 31 of the 2⁵ -m-sequence. One obtains the 2⁵ -m-sequenceas a binary sequence of numbers:

    c.sub.0 (n)={0000100101100111110001101110101},             (4)

which is identical to the contents of the stage 6.

An inadequacy of the digital signals produced with the known shiftregister is that they have a period of 2^(n) -1 where n denotes thenumber of stages of the shift register. Thus in the case of the depicted2⁵ -m-sequence the period duration is 31. Therefore, the thus generateddigital signals are not easily suited for further digital processingusing customary digital measured-value processing devices. This is true,for example, when a fast Fourier transform is supposed to be made, forwhich it is a condition that the data record has 2^(n) values.

SUMMARY OF THE INVENTION

The present invention proposes a feedback shift register for generatingdigital signals representing pseudo-random number sequences, whichalways supply a full data record 2^(n) regardless of the number of itsn-stages.

In the case of a feedback shift register of the type according to theinvention indicated at the outset, this objective is achieved in thatthe clock-pulse generator is linked with the n-stages via a controllablegate circuit, which blocks one clock pulse of 2^(n) clock pulses of theclock-pulse generator in each case.

An essential advantage of the shift register according to the inventionconsists in that as the result of the blocking or suppressing of oneclock pulse from a series of 2^(n) clock pulses of the clock-pulsegenerator in each case, the shift register is not clocked further forone pulse of the clock pulse generator, so that the stages of the shiftregister do not change their state for this one clock pulse; as aresult, the generated digital signals are extended by one bit and thethus acquired pseudo-random number sequence or the thus acquired digitalsignals have a period duration of 32, when the consideration is based ona 5-stage register. In the case of a 4-stage shift register, a periodduration of 16 would result, when one proceeds in accordance with theinvention. The spectrum of such an extended sequence is only marginallychanged compared to a sequence that has not been extended, so that interms of measurement techniques, no adverse influences arise in theprocessing of such digital signals. It should also be mentioned--asalready revealed by the above explanations--that the invention is notlimited to irreducible polynomials of the 5th degree.

In the case of the shift register according to the invention, thecontrollable gate circuit can be designed in different ways, as long asit permits one out of the 2^(n) clock pulses of the clock pulsegenerator to be gated in each case. It is considered to be advantageousfor the controllable gate circuit to contain a gate element having twoinputs, whose one input is linked to the clock-pulse generator, andwhose other input is linked to a control circuit, and for the controlcircuit to block the gate element by emitting a control signal in eachcase during 2^(n) clock pulses for the duration of one clock pulse. Thiscan be achieved, for example, by means of a counting circuit, which isacted upon by the clock-pulse generator.

To achieve the least complex possible circuit engineering, it is deemedespecially advantageous for the control circuit to be made up of adigital circuit module that is connected on the input side to then-stages of the shift register and, given a preselected contents ofthese stages, for it to generate the control signal, and for the outputof the digital circuit module to be connected to the other input of thegate element.

In the case of the shift register according to the invention, the gateelement can be constituted quite simply in terms of circuit engineeringby an AND gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a known shift register arrangement.

FIG. 2 illustrates the various states for the shift register of FIG. 1.

FIG. 3 is an example of a shift register according to an embodiment ofthe invention.

FIG. 4 illustrates a representation of the pulses occurring in theembodiment of FIG. 3.

FIG. 5 illustrates a list in tabular form of the states of the stagecontents of the shift register according to FIG. 3.

DETAILED DESCRIPTION

The structure of the shift register 10 depicted in FIG. 3 corresponds tothat of FIG. 1 in so far as it is likewise provided with five stages 11,12, 13, 14 and 15, a feedback via an exclusive OR gate 16 taking placehere as well. Assigned here as well to the shift register 10 is aclock-pulse generator 17, which, however, is not connected directly tothe clock inputs of the individual stages 11 through 15 of the shiftregister 10, but rather via a controllable gate circuit 18. Theclock-pulse generator 17 emits clock pulses CLK. In the depictedexemplary embodiment, the gate circuit 18 is a control circuit that hasa gate element 19 designed as an AND gate and a pulse generator 20. Thispulse generator 20 can be designed as a counting circuit, which islinked directly with the clock-pulse generator 17 and which, given adefined counter content, emits an output signal as a control signal G.However, the control circuit can also be comprised of a digital circuitmodule, which is connected to the stages of the shift register 10 andwhich emits the control signal G at a defined state of these stages.

As FIG. 4 shows, following a freely specifiable, but definite number ofpulses CLK from the clock-pulse generator 17, the pulse generator 20emits the control signal G, by means of which the AND-gate 19 is blockedfor a clock pulse CLK. The clock pulses CLK' occur then at the output ofthe controllable gate circuit 18. This means that the shift register 10is not advanced for one clock pulse of the clock pulse generator 17, sothat the states of the individual stages of the shift register 10 retaintheir state for this one clock pulse. The generated 2⁵ -m-sequence isconsequently extended by 1 bit.

This factual situation is also clearly revealed by FIG. 5, in which thestates of the individual stages 11 through 15 of the shift register 10are depicted--similarly to in FIG. 2 for the known shift register.

The rows 2 and 3 of the table in accordance with FIG. 5 show clearly,namely, that the state x¹ mod G_(KKF) (X) is obtained two times, so thata period of 32 results in the case of the depicted 5-stage shiftregister.

What is claimed is:
 1. A circuit for generating digital signalsrepresenting pseudo-random sequences comprising:a feedback shiftregister including n-stages and exclusive OR-circuits in the feedbacklogic; a clock-pulse generator; and a controllable gate circuit linkingsaid clock pulse generator and said feedback shift register and blockingone clock pulse of every 2^(n) clock pulses of the clock-pulsegenerator.
 2. The circuit of claim 1, wherein said controllable gatecircuit contains a gate element having two inputs, one said input beinglinked to the clock-pulse generator, and the other input being linked toa control circuit, said control circuit blocking the gate element byemitting a control signal for the duration of one clock pulse duringevery 2^(n) clock pulses of the clock-pulse generator.
 3. The circuit ofclaim 2, wherein said control circuit is made up of a digital circuitmodule, which has an input connected to the n-stages of said shiftregister and, given a preselected contents of these stages, generatesthe control signal, and that the output of the digital circuit module isconnected to the other input of the gate element.
 4. The circuit ofclaim 1, wherein the gate element is an AND gate.
 5. The circuit ofclaim 2, wherein the gate element is an AND gate.
 6. The circuit ofclaim 3, wherein the gate element is an AND gate.